Memory Controller, Memory System Including the Same, and Method for Operating the Same

ABSTRACT

A memory controller includes a first interface unit, a processor, a randomization unit, a state conversion unit, and a second interface unit. The first interface unit exchanges data with an external device, and the processor determines whether to randomize or state-convert the received data. The randomization unit randomizes data received through the first interface unit in response to the processor and generates randomization information in response to the randomization operation. The state conversion unit state-converts data received through the first interface unit in response to the processor and generates conversion information in response to the state conversion operation. The second interface unit receives the randomized data and the randomization information from the randomization unit, receives the state-converted data and the conversion information from the state conversion unit, and exchanges at least one of the randomized data, the randomization information, the state-converted data and the conversion information with a memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. Ser. No. 12/777,676, filed onMay 11, 2010 (Now U.S. Pat. No. 8,549,328), which claims priority under35 U.S.C. §119 to Korean Patent Application No. 10-2009-0043149, filedon May 18, 2009, the disclosures of which are hereby incorporated byreference.

BACKGROUND

The present disclosure herein relates to semiconductor memory devices,and more particularly, to nonvolatile memory devices.

Semiconductor memory devices are memory devices that are implementedusing a semiconductor, such as silicon. The semiconductor memory devicesare classified into volatile memory devices and nonvolatile memorydevices.

Volatile memory devices lose data stored therein when power supplythereto is interrupted. Examples of volatile memory devices includestatic random access memory (SRAM) devices, dynamic random access memory(DRAM) devices, and synchronous dynamic random access memory (SDRAM)devices. Nonvolatile memory devices retain data stored therein even whenpower supply thereto is interrupted. Examples of nonvolatile memorydevices include read-only memory (ROM) devices, programmable read-onlymemory (PROM) devices, erasable programmable read-only memory (EPROM)devices, electrically erasable programmable read-only memory (EEPROM)devices, flash memory devices, phase-change random access memory (PRAM)devices, magnetic random access memory (MRAM) devices, resistive randomaccess memory (RRAM) devices, and ferroelectric random access memory(FRAM) devices. The flash memory devices are classified into NOR-typeflash memory devices and NAND-type flash memory devices.

SUMMARY

A memory controller according to some embodiments includes a firstinterface unit configured to exchange data with an external device; aprocessor configured to determine, in response to data received throughthe first interface unit, whether to randomize or state-convert thereceived data; a randomization unit configured to randomize first datareceived through the first interface unit in response to the control ofthe processor and to generate randomization information in response tothe randomization operation; a state conversion unit configured tostate-convert second data received through the first interface unit inresponse to the control of the processor and to generate conversioninformation in response to the state conversion operation; and a secondinterface unit configured to receive the randomized first data and therandomization information from the randomization unit, receive thestate-converted second data and the conversion information from thestate conversion unit, and exchange at least one of the randomized data,the randomization information, the state-converted data and theconversion information with a memory.

In some embodiments, the randomization unit is configured to restore therandomized first data to the original first data using the randomizationinformation received through the second interface unit in response toreceiving the randomized first data and the randomization informationthrough the second interface unit.

In other embodiments, the state conversion unit is configured to restorethe state-converted second data to the original data using theconversion information received through the second interface unit inresponse to receiving the state-converted second data and the conversioninformation through the second interface unit.

In further embodiments, the randomization unit is configured to generatea random sequence in response to a predetermined seed, to perform alogical operation on the random sequence and the received first data, tooutput the results of the logical operation as the randomized firstdata, and to output the predetermined seed as the randomizationinformation.

In still further embodiments, the state conversion unit is configured tocounts the number of the respective logic states of the received seconddata, to compare the number of the first logic states of the receivedsecond data and the number of the second logic states of the receivedsecond data, and to exchange the first logic states and the second logicstates in response to the comparison results.

In still further embodiments, the state conversion unit converts thereceived second data such that the number of the highest logic statesamong the received second data becomes smaller than the number of theother respective logic states.

In still further embodiments, the state conversion unit converts thereceived second data such that the number of the lowest logic statesamong the received second data becomes smaller than the number of theother respective logic states.

In still further embodiments, in response to receiving second data withfirst and second logic states through the first interface unit, thestate conversion unit is configured to count the number of the firstlogic states and the second logic states of the received second data andto invert the received second data in response to the number of thefirst logic states being smaller than the number of the second logicstates.

In still further embodiments, the processor determines to randomize thereceived data when the received data correspond to sequential data.

In still further embodiments, the processor determines to state-convertthe received data when the received data correspond to random data.

A memory system according to some embodiments includes a nonvolatilememory device and a memory controller configured to control thenonvolatile memory device. The memory controller includes a firstinterface unit configured to exchange data with an external device; aprocessor configured to determine, in response to data received throughthe first interface unit, whether to randomize or state-convert thereceived data; a randomization unit configured to randomize first datareceived through the first interface unit in response to the control ofthe processor and to generate randomization information in response tothe randomization operation; a state conversion unit configured tostate-convert second data received through the first interface unit inresponse to the control of the processor and to generate conversioninformation in response to the state conversion operation; and a secondinterface unit configured to receive the randomized first data and therandomization information from the randomization unit, receive thestate-converted second data and the conversion information from thestate conversion unit, and exchange data with the nonvolatile memorydevice.

In some embodiments, the nonvolatile memory device and the controllerforms a solid state drive (SSD).

In other embodiments, the nonvolatile memory device and the controllerforms a memory card.

Methods for operating a memory controller according to some embodimentsinclude receiving data from an external device; determining whether toperform a randomization operation or a state conversion operation on thebasis of the received data; and randomizing or state-converting thereceived data in response to the determination results.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the inventive concept, and are incorporated in andconstitute a part of this specification. The drawings illustrateexemplary embodiments of the inventive concept and, together with thedescription, serve to explain principles of the inventive concept. Inthe drawings:

FIG. 1 is a block diagram of a memory system according to someembodiments;

FIG. 2 is a block diagram of a nonvolatile memory device of FIG. 1according to some embodiments;

FIG. 3 is a block diagram of a controller of FIG. 1 according to someembodiments;

FIG. 4 is a flow chart illustrating operations of the controller of FIG.3 according to some embodiments;

FIG. 5 is a block diagram of a randomization unit of FIG. 3 according tosome embodiments;

FIG. 6 is a diagram illustrating a storage region of a memory cell arrayof the flash memory device of FIG. 2 according to some embodiments;

FIGS. 7 to 10 are diagrams illustrating state conversion operations ofthe controller of FIG. 3 according to some embodiments;

FIGS. 11 to 13 are diagrams illustrating state conversion operations ofthe controller of FIG. 3 according to further embodiments;

FIG. 14 is a block diagram of the flash memory device of FIG. 2according to further embodiments;

FIG. 15 is a diagram illustrating loading data into a flash memorydevice in a multi-plain program and state conversion operationsaccording to some embodiments;

FIG. 16 is a diagram illustrating loading data into the flash memorydevice in a multi-plain program and state conversion operationsaccording to further embodiments;

FIG. 17 is a block diagram of the flash memory device of FIG. 1according to further embodiments; and

FIG. 18 is a block diagram of a computing system including the memorysystem of FIG. 1 according to some embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram of a memory system according to someembodiments.

Referring to FIG. 1, a memory system 10 according to some embodimentsincludes a controller 100 and a nonvolatile memory device 200.

The controller 100 is connected to a host and the nonvolatile memorydevice 200. The controller 100 is configured to transfer data that isread from the nonvolatile memory device 200 to the host and store datathat is received from the host in the nonvolatile memory device 200. Thecontroller 100 will be described later in detail with reference to FIG.3.

The nonvolatile memory device 200 may include a memory cell array forstoring data, a read/write circuit for reading/writing data from/in thememory cell array, an address decoder for decoding an address receivedfrom an external device and transferring the same to the read/writecircuit, and a control logic circuit for controlling an overalloperation of the nonvolatile memory device 200. The nonvolatile memorydevice 200 will be described later in detail with reference to FIGS. 2and 17.

The controller 100 and the nonvolatile memory device 200 may beintegrated into one semiconductor device. As an example, the controller100 and the nonvolatile memory device 200 may be integrated into onesemiconductor device to constitute a memory card. For example, thecontroller 100 and the nonvolatile memory device 200 may be integratedinto one semiconductor device to constitute a PC card (e.g., PCMCIA(Personal Computer Memory Card International Association)), a compactflash card (CF), a smart media card (SM/SMC), a memory stick, amultimedia card (e.g., MMC, RS-MMC and MMCmicro), a SD card (e.g., SD,miniSD, and microSD), or a universal flash storage (UFS).

As another example, the controller 100 and the nonvolatile memory device200 may be integrated into one semiconductor device to constitute asolid state drive (SSD). For example, the SSD may include a device thatis configured to store data in a semiconductor memory. When the memorysystem 10 is used as an SSD, the operation speed of the host connectedto the memory system 10 may increase remarkably.

As another example, the memory system 10 may be applicable to computers,UMPCs (Ultra Mobile PCs), workstations, net-books, PDAs (PersonalDigital Assistants), portable computers, web tablets, wireless phones,mobile phones, smart phones, digital cameras, digital audio recorders,digital audio players, digital picture recorders, digital pictureplayers, digital video recorders, digital video players, devices capableof transmitting/receiving information in wireless environments, one ofvarious electronic devices constituting a home network, one of variouselectronic devices constituting a computer network, one of variouselectronic devices constituting a telematics network, or one of variouscomponents (e.g., an SSD and a memory card) constituting a computingsystem.

As another example, the nonvolatile memory device 200 or the memorysystem 10 may be mounted in various types of packages. Examples of thepackages of the nonvolatile memory device 200 or the memory system 10include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip ScalePackages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic DualIn-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip OnBoard (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric QuadFlat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline IntegratedCircuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small OutlinePackage (TSOP), System In Package (SIP), Multi Chip Package (MCP),Wafer-level Fabricated Package (WFP), and Wafer-level processed StackPackage (WSP).

FIG. 2 is a block diagram of the nonvolatile memory device 200 of FIG. 1according to some embodiments.

Referring to FIG. 2, the nonvolatile memory device 200 includes a memorycell array 210, an address decoder 220, a read/write circuit 230, a datainput/output (I/O) circuit 240, and a control logic circuit 250.

The memory cell array 210 is connected through word lines WL to theaddress decoder 220 and is connected through bit lines BL to theread/write circuit 230. The memory cell array 210 includes a pluralityof memory cells. For example, rows of the memory cells are connected tothe word lines WL, and columns of the memory cells are connected to thebit lines BL. For example, the memory cells are configured to store oneor more bits per cell,

The address decoder 220 is connected through the word lines WL to thememory cell array 210. The address decoder 220 operates in response tothe control of the control logic circuit 250. The address decoder 220receives an address ADDR from an external device. For example, theaddress ADDR is received from the controller 100 of FIG. 1.

The address decoder 220 decodes a row address among the receivedaddresses ADDR and selects the word lines WL according to the decodedrow address. The address decoder 220 decodes a column address among thereceived addresses ADDR and transfers the decoded column address to theread/write circuit 230. For example, the address decoder 220 includes arow decoder, a column decoder, and an address buffer.

The read/write circuit 230 is connected through the bit lines BL to thememory cell array 210 and is connected through data lines DL to the dataI/O circuit 240. The read/write circuit 230 operates in response to thecontrol of the control logic circuit 250. The read/write circuit 230receives the decoded column address from the address decoder 220 andselects the bit lines BL according to the decoded column address.

For example, the read/write circuit 230 receives data from thecontroller 100 and stores the received data in the memory cell array210. As another example, the read/write circuit 230 reads data from thememory cell array 210 and transfers the read data to the data I/Ocircuit 240. As another example, the read/write circuit 230 reads datafrom a first storage region of the memory cell array 110 and writes theread data in a second storage region of the memory cell array 210. Forexample, the read/write circuit 230 performs a copy-back operation.

For example, the read/write circuit 230 includes a page buffer and acolumn selection circuit. As another example, the read/write circuit 230includes a sense amplifier, a write driver, and a column selectioncircuit.

The data I/O circuit 240 is connected through the data lines DL to theread/write circuit 230. The data I/O circuit 240 operates in response tothe control of the control logic circuit 250. The data I/O circuit 240exchanges data with an external device. For example, the data I/Ocircuit 240 exchanges data with the controller 100 of FIG. 1. Datareceived from an external device are transferred through the data linesDL to the read/write circuit 230. Data received from the read/writecircuit 230 are outputted to an external device. For example, the dataI/O circuit 240 includes a data buffer.

The control logic circuit 250 is connected to the address decoder 220,the read/write circuit 230, and the data I/O circuit 240. The controllogic circuit 250 controls an overall operation of the nonvolatilememory device 200. The control logic circuit 250 operates in response toa control signal CTRL received from an external device. For example, thecontrol signal CTRL is received from the controller 100 of FIG. 1.

Hereinafter, it is assumed that the nonvolatile memory device 200 is aflash memory device. However, it will be understood that the nonvolatilememory device 200 is not limited to being a flash memory device. Forexample, it will be understood that the nonvolatile memory device 200may be configured using nonvolatile memories such as EPROMs, EEPROMs,flash memories, PRAMs, MRAMs, FRAMs, and RRAMs.

Hereinafter, it is assumed that the flash memory device 200 isconfigured to store two bits in a memory cell. For example, the flashmemory device 200 may include multi-level cells that are configured tostore a least significant bit (LSB) and a most significant bit (MSB) ina memory cell. A memory cell may be programmed to one of four logicstates. The logic states programmed in a memory cell may be discerned bythe threshold voltage of the memory cell.

The memory cells connected to a word line may form two logic pages. Forexample, the LSBs of memory cells connected to a word line may form aleast significant page. The MSBs of memory cells connected to a wordline may form a most significant page.

However, it will be understood that the flash memory device 200 is notlimited to storing two bits in a memory cell. For example, it will beunderstood that the flash memory device 200 may be configured to storeone bit in a memory cell, As another example, it will be understood thatthe flash memory device 200 may be configured to store an LSB, an MSBand at least one central significant bit (CSB) in a memory cell.

For example, it is assumed that the flash memory device 200 supports arandom write operation and a random read operation. The random writeoperation may be an operation of writing, in the flash memory device200, data smaller than the page of the flash memory device 200. Therandom read operation may be an operation of reading, from the flashmemory device 200, data smaller than the page of the flash memory device200.

It is illustrated in FIG. 2 that the flash memory device 200 includesone memory cell array 210 and one read/write circuit 230. However, itwill be understood that the flash memory device 200 may include aplurality of memory cell arrays and a plurality of read/write circuits.For example, the flash memory device 200 may include a plurality ofplanes that can be read and written independently.

FIG. 3 is a block diagram of the controller 100 of FIG. 1 according tosome embodiments.

Referring to FIG. 3, the controller 100 includes a system bus 110, aprocessor 120, a RAM 130, an error correction unit 140, a host interface150, a memory interface 160, and an encoding/decoding unit 170.

The system bus 110 provides a channel between the components of thecontroller 100. The processor 120 accesses the components of thecontroller 100 through the system bus 110. The processor 120 may controlthe components of the controller 100. The processor 120 may control anoverall operation of the controller 100.

The RAM 130 is connected to the system bus 110. For example, the RAM 130may be used as a working memory of the controller 100. For example, thesoftware driven by the processor 120 may be loaded into the RAM 130. Forexample, the components of the controller 100 may perform apredetermined operation by means of the RAM 130. For example, the RAM130 may be used as a buffer memory. For example, data transferredthrough the controller 100 to the flash memory device 200 may betemporarily stored in the RAM 130. Data transferred from the flashmemory device 200 through the controller 100 to the host may betemporarily stored in the RAM 130.

The error correction unit 140 is connected to the system bus 110. Theerror correction unit 140 may be configured to correct an error in dataread from the flash memory device 200. For example, the error correctionunit 140 may generate error check data for user data to be written inthe flash memory device 200. The user data and the error check data maybe stored in the flash memory device 200. When the user data and theerror check data are read from the flash memory device 200, the errorcorrection unit 140 may detect and correct an error in the read userdata by means of the read error check data.

For example, the error check data may include CRC (Cyclic RedundancyCheck) data, BCH (Bose, Chaudhuri, and Hocquenghem) data, and RS(Reed-Solomon) data. For example, the error correction unit 140 may beimplemented in hardware as a digital circuit, an analog circuit, or acombination thereof. As another example, the error correction unit 140may be implemented in software. As another example, the error correctionunit 140 may be implemented in a combination of hardware and software.

The host interface 150 interfaces with the host. The host interface 150may include a protocol for communication with the host. For example, thehost interface 150 may include one of various interface protocols suchas USB (Universal Serial Bus), MMC (Multimedia Card), PCI (PeripheralComponent Interface), PCI-E (PCI-Express), ATA (Advanced TechnologyAttachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer SmallInterface), ESDI (Enhanced Small Disk Interface), and IDE (IntegratedDrive Electronics).

The memory interface 160 interfaces with the flash memory device 200.The memory interface 160 may include a protocol for communication withthe flash memory device 200. For example, the memory interface 160 mayinclude a NAND protocol.

The encoding/decoding unit 170 is connected to the system bus 110. Theencoding/decoding unit 170 is configured to encode data received throughthe host interface 150 from the host. The encoded data are transferredthrough the memory interface 160 to the flash memory device 200. Theencoding/decoding unit 170 is configured to decode data received throughthe memory interface 160 from the flash memory device 200. The decodeddata are outputted through the host interface 150.

The encoding/decoding unit 170 includes a randomization unit 171 and astate conversion unit 175. The randomization unit 171 is configured torandomize (hereinafter referred to as random-encode) data receivedthrough the host interface 150. The randomization unit 171 is configuredto restore (hereinafter referred to as random-decode) data, receivedthrough the memory interface 160, to the original data. Therandomization unit 171 is configured to state-convert (hereinafterreferred to as state-encode) data received through the host interface150. The randomization unit 171 is configured to restore (hereinafterreferred to as state-decode) data, received through the memory interface160, to the original data.

For example, the encoding/decoding unit 170 may be implemented in adigital circuit, an analog circuit, or a combination thereof. As anotherexample, the encoding/decoding unit 170 may be implemented in softwaredriven in the processor 120. As another example, the encoding/decodingunit 170 may be implemented in a combination of hardware and software.

FIG. 4 is a flow chart illustrating an operation of the controller 100of FIG. 3 according to some embodiments.

Referring to FIGS. 3 and 4, data are received in step S110. For example,data are received through the host interface 150 from the host. Asanother example, data are received through the memory interface 160 fromthe flash memory device 200. For example, the received data aretemporarily stored in the RAM 130.

In step S120, it is determined whether to perform a randomizationoperation. For example, it is assumed that data are received from thehost. On the basis of the received data, the processor 120 determineswhether to random-encode or state-encode the received data. For example,if the received data are sequential data, the processor 120 determinesthat a random-encode operation is to be performed. The sequential datameans data of a size equal to or larger than the unit of a writeoperation of the flash memory device 200.

The unit of a write operation of the flash memory device 200 is a page.That is, if the size of the received data is equal to or larger than thestorage capacity of one page of the flash memory device 200, theprocessor 120 determines that a random-encode operation is to beperformed. The random-encode operation is performed using apredetermined seed, The random-encode operation improves the reliabilityof data written in the flash memory device 200.

As another example, if the received data are random write data, theprocessor 120 determines that a state-encode operation is to beperformed. The random write data means data of a size smaller than theunit of a write operation of the flash memory device 200. The unit of awrite operation of the flash memory device 200 is a page. If the size ofthe received data is smaller than the storage capacity of one page ofthe flash memory device 200, the processor 120 determines that astate-encode operation is to be performed. The state-encode operationincludes an operation of exchanging the logic states of the receiveddata. The state-encode operation improves the reliability of datawritten in the flash memory device 200.

As another example, if data are received from the flash memory device200, the encoding/decoding unit 170 performs a random-decode operationor a state-decode operation. If the received data are sequential data,the randomization unit 171 performs a random-decode operation. If thereceived data are random data, the state conversion unit 175 performs astate-decode operation.

The random-encode/decode operation will be described later in detailwith reference to FIG. 5. The state-encode/decode operation will bedescribed later in detail with reference to FIGS. 7 to 10.

If it is determined in step S120 that a randomization operation is notto be performed, the controller 100 proceeds to step S130. In step S130,the state of the received data is converted. For example, the stateconversion unit 175 of the encoding/decoding unit 170 state-encodes thereceived data. Thereafter, conversion information CI is generated instep S180. The conversion information CI indicates how the logic statesof the received data have been exchanged. The conversion information CImay be generated by the state conversion unit 175.

Thereafter, in step S190, the state-converted data and the conversioninformation CI are outputted as encoded data. For example, thestate-converted data and the conversion information CI are outputtedthrough the memory interface 160 to the flash memory device 200. Thatis, the state-converted data and the conversion information CI arewritten in the flash memory device 200.

If it is determined in step S120 that a randomization operation is to beperformed, the controller 100 proceeds to step S140. In step S140, thereceived data are random-encoded. For example, the randomization unit171 of the encoding/decoding unit 170 random-encodes the received data.In step S150, randomization information RI is generated. Therandomization information RI indicates how the received data have beenrandomized. For example, the randomization information RI includes aseed used in the randomization operation. For example, the randomizationinformation RI is generated by the randomization unit 171.

In step S160, it is determined whether to state-convert spare data. Forexample, the spare data include data necessary to write/read user datain/from the flash memory device 200. For example, the spare data includea seed used in the randomization operation.

The seed is data necessary to perform a random-encode/decode operation.That is, in a random-encode operation, it is assumed that both of theuser data and the spare data are random-encoded and the results arestored in the flash memory device 200. In a read operation, therandom-encoded user data and spare data are read from the flash memorydevice 200. A seed is necessary to perform a random-decode operation.The seed is included in the random-encoded spare data. Thus, if the seedis random-encoded, a random-decode operation is impossible to perform.

If the spare data including a seed are not random-encoded, the sparedata have a lower reliability than the random-encoded user data.According to some embodiments, the controller 100 performs astate-conversion operation on the spare data to improve the reliabilityof the spare data.

If it is determined in step S160 that the spare data are to bestate-converted, the controller 100 proceeds to step S170; and if not,the controller 100 proceeds to step S190. Whether to state-convert thespare data may be determined considering the reliability, degradationand program/read time of the flash memory device 200. For example, ifthe program/erase count is smaller than a predetermined value, the sparedata may not be state-converted; and if the program/erase count isgreater than the predetermined value, the spare data may bestate-converted.

In step S170, the spare data are state-encoded. The state conversionunit 175 may state-encode the spare data including a seed. In step S170,the state-encoded data are not limited to being spare data. For example,the state-encoded data include data that are not random-encoded. In step180, conversion information CI is generated. The conversion informationCI may be generated by the state conversion unit 175.

In step S190, the random-encoded data, the randomization information RI,the state-encoded data, and the conversion information CI are outputtedas encoded data. For example, the encoded data are outputted through thememory interface 160 to the flash memory device 200. That is, theencoded data are written in the flash memory device 200.

FIG. 5 is a block diagram of the randomization unit 171 of FIG. 3according to an embodiment of the inventive concept.

Referring to FIGS. 3 and 5, the randomization unit 171 includes a shiftregister 172 and an operation circuit 174.

The shift register 172 receives a seed and a clock CLK. The shiftregister 172 is configured to store the seed. The shift register 172shifts the stored seed in response to the clock CLK.

For example, it is assumed that the seed is ‘1011’. When receiving afirst clock, the shift register 172 outputs ‘1’ and stores ‘1101’. Whenreceiving a second clock, the shift register 172 outputs ‘1’ and stores‘1110’. When receiving a third clock, the shift register 172 outputs ‘0’and stores ‘0111’. When receiving a fourth clock, the shift register 172outputs ‘1’ and stores ‘1011’.

That is, if the seed is 4-bit data, the seed cycles in the shiftregister 172 during the input of the first to fourth clocks. Also, theseed is outputted on a bit-by-bit basis during the cycle of the seed.The output of the shift register 172 is used as a random sequence RS.The random sequence RS is transferred to the operation circuit 174.

For example, the clock CLK provided to the randomization unit 171 may besynchronized with a clock provided to the memory interface 160. Forexample, the clock CLK provided to the randomization unit 171 may be asystem clock of the controller 100. As another example, the clock CLKprovided to the randomization unit 171 may be an internal clockgenerated from the system clock of the controller 100.

The operation circuit 174 receives the random sequence RS from the shiftregister 172. The operation circuit 174 receives page data PD. Forexample, the page data PD may be received from the host interface 150.That is, the page data PD may be write data received from the host. Asanother example, the page data PD may be received from the memoryinterface 160. That is, the page data PD may be read data received fromthe flash memory device 200.

The operation circuit 174 may be configured to logically operate thepage data PD and the random sequence RS. For example, the operationcircuit 174 may be configured to output the XOR (eXclusive OR) value ofthe page data PD and the random sequence RS. For example, if the pagedata PD are write data, the output of the operation circuit 174 may berandom-encoded page data RD. The random-encoded page data RD may bestored in the flash memory device 200.

For example, the seed may be data retained in the randomization unit171. For example, the randomization unit 171 may store a plurality ofseeds in a table. For example, a specific seed may be selected among thestored seeds on the basis of received data. For example, a specific seedmay be selected among the stored seeds on the basis of an addressreceived from the host. For example, a specific seed may be selectedamong the stored seeds according to the frequency of program/eraseoperations. As another example, the seed may be randomly-generated data.

As another example, if the page data PD are read data, the page data PDmay be random-encoded data. The operation circuit 174 may decode thepage data PD to output the original data. For example, if the page dataPD are read data, the randomization unit 171 may decode the page data PDby means of the spare data read from the flash memory device 200together with the page data PD. The randomization unit 171 may detectthe seed from the read spare data.

For example, the read spare data may be state-decoded by the stateconversion unit 175. The state-decoded spare data may be transferred tothe randomization unit 171. The randomization unit 171 may detect theseed from the state-decoded spare data. The detected seed may beprovided to the shift register 172. That is, the randomization unit 171may random-decode the page data PD by means of the seed used in therandom encode operation.

For example, the output of the operation circuit 174 may be transferredto the host. As another example, the output of the operation circuit 174may be updated and random-encoded and the results may be stored in theflash memory device 200. For example, the data read from the flashmemory device 200 may be copied back.

A program operation of the flash memory device 200 may be performed byF-N tunneling or hot electron injection. In the program operation of theflash memory device 200, an electric charge may be transferred through atunnel insulating layer to a charge storage layer. Thus, the tunnelinsulating layer may degrade as the program operation repeats. Thedegradation of the tunnel insulating layer may change the programcharacteristics of the corresponding memory cell.

The amount of the electric charge transferred to the charge storagelayer of the corresponding memory cell may increase with an increase inthe threshold voltage level of the programmed memory cell. That is, thedegradation degree of the corresponding memory cell may increase with anincrease in the threshold voltage level of the programmed memory cell.For example, it is assumed that a first memory cell is repeatedlyprogrammed to a first threshold voltage and a second memory cell isrepeatedly programmed to a second threshold voltage higher than thefirst threshold voltage. Herein, the first and second memory cells maydiffer in their degradation degrees. For example, the degradation degreeof the second memory cell may be greater than the degradation degree ofthe first memory cell.

That is, if the memory cells are repeatedly programmed in the same datapattern, they may differ in their degradation degrees.

If the memory cells differ in their degradation degrees, they may differin their program characteristics, thus increasing the probability of aprogram error or a read error in the memory cells.

The randomization unit 171 logically operates the page data PD togenerate randomized data RD. The logical operation is performed using aselected seed. Thus, even when the page data PD of the same pattern arereceived, the pattern of the random-encoded page data RD may varyaccording to the selected seed. The randomized data are written in theflash memory device 200. Thus, the data of the same pattern areprevented from being repeatedly written in the flash memory device 200.That is, the flash memory device 200 improves in reliability.

As time passes, a charge loss may occur in the charge storage layer ofthe memory cell of the flash memory device 200. If the charge lossincreases above a predetermined level, a read error may occur in thecorresponding memory cell. It is assumed that a first memory cell with afirst threshold voltage is adjacent to a second memory cell with asecond threshold voltage lower than the first threshold voltage. Thestrength of the electric field between the first memory cell and thesecond memory cell may increase with an increase in the differencebetween the first threshold voltage and the second threshold voltage.The level of a charge loss in the first memory cell may increase with anincrease in the strength of the electric field between the first memorycell and the second memory cell. That is, the probability of a readerror in the first memory cell may increase with an increase in thethreshold voltage difference between the adjacent first and secondmemory cells.

It will be understood that the seed may be selected to reduce thethreshold voltage difference between the adjacent memory cells below apredetermined value. In this case, it will be understood that therandom-encoded page data RD may improve in reliability.

As described above, when received data are sequential data, the receiveddata are randomized. Thus, it will be understood that the data writtenin the flash memory device 200 may improve in reliability.

It has been described in the above embodiments that the spare data ofthe randomized data are state-converted. However, it will be understoodthat the state conversion operation of the spare data of the randomizeddata may be omitted to improve the operation speed of the memory system10. In this case, the seed may be detected from the spare data without astate-decode operation.

FIG. 6 is a diagram illustrating a storage region of the memory cellarray 210 of the flash memory device 200 of FIG. 2 according to someembodiments.

In the example illustrated in FIG. 6, it is assumed that the storageregion illustrated in FIG. 6 is a page, and that the address of data inthe storage region increases from the left toward the right of the page.

It is further assumed that a program operation is performed on aspecific region RA in the page of FIG. 6. That is, it is assumed that arandom read/write operation is performed on the specific region RA. Itis assumed that the specific region A is comprised of ‘n’ bits, andaddress regions before the specific region RA are comprised of ‘m’ bits.

In a read/write operation, data are encoded/decoded by the randomizationunit 171. As described in FIG. 5, a random-encode/decode operation isperformed using random sequences RS that are sequentially generated inresponse to the clock CLK. For example, the random sequences RS may besequentially generated in response to an address count-up. Thus, (m+n)random sequences RS are necessary to random-encode/decode the specificregion RA. Herein, the ‘m’ random sequences RS may be disregarded andthe ‘n’ random sequences RS may be used to random-encode/decode thespecific region RA.

As described above, in a random read/write operation, (m+n) randomsequences are necessary to access the specific region RA comprised of‘n’ bits, (m+n) clocks CLK are necessary to generate the (m+n) randomsequences. Thus, a time delay may occur if a randomization operation isperformed in a random write/read operation. In order to overcome theabove problem, the memory system 10 of FIG. 1 according to someembodiments performs a state-encode/decode operation in a randomread/write operation.

FIGS. 7 to 10 are diagrams illustrating state conversion operations ofthe controller 100 of FIG. 3 according to some embodiments.

In FIG. 7, the axis of abscissas (x-axis) represents logic states andthe axis of ordinates (y-axis) represents the number of data. Each ofthe logic states is comprised of two bits. When data are programmed in amemory cell, the threshold voltage of the memory cell may be determinedaccording to the logic state represented by the data.

An erase state E and first to third program states P1˜P3 are illustratedin FIG. 7. For example, it is assumed that the lowest to highest logicstates are represented along the direction of the axis of abscissas(x-axis). For example, it is assumed that the erase state E representsthe lowest logic state and the third program state P3 represents thehighest logic state.

For example, it is assumed that, when data are programmed in the flashmemory device 200, the threshold voltage corresponding to the firstprogram state P1 is higher than the threshold voltage corresponding tothe erase state E, the threshold voltage corresponding to the secondprogram state P2 is higher than the threshold voltage corresponding tothe first program state P1, and the threshold voltage corresponding tothe third program state P3 is higher than the threshold voltagecorresponding to the second program state P2.

The logic states illustrated in FIG. 7 represent the logic states ofdata received from the host. Referring to FIG, 7, the number of statesdecreases in the order of the third program state P3 , the erase stateE, the first program state P1 and the second program state P2.

When data corresponding to the states illustrated in FIG. 7 areprogrammed in the flash memory device 200, the threshold voltagecorresponding to the third program state P3 is the highest among thethreshold voltages corresponding to the four logic states E and P1˜P3.Thus, the memory cells programmed to the third program state P3 may bemost strongly influenced by the effect of a charge loss. Also, thememory cells programmed to the third program state P3 may transfer thecoupling effects to the adjacent memory cells most strongly.

The threshold voltage corresponding to the erase state E is the lowestamong the threshold voltages corresponding to the four logic states Eand P1˜P3. Thus, in a read operation, the memory cells programmed to theerase state E may be most strongly stressed by a read voltage. That is,the memory cells programmed to the erase state E may be most stronglyinfluenced by the effect of a read voltage disturbance.

The state conversion unit 175 may convert the state of program data sothat the amount of data corresponding to the third program state P3 andthe erase state E (among program data) becomes smaller than the amountof data corresponding to the first and second program states P1 and P2.

FIG. 8 is a diagram illustrating program operations of the flash memorydevice 200 according to some embodiments.

In FIG. 8, the axis of abscissas (x-axis) represents voltages and theaxis of ordinates (y-axis) represents the number of memory cells. Thatis, FIG. 8 illustrates the threshold voltage distribution of the memorycells of the flash memory device 200.

A program operation of the flash memory device 200 includes twooperation steps. First, when LSB data are received, an LSB programoperation is performed. In the LSB program operation, memory cells areprogrammed to have an erase state E or a program state P. For example,it is illustrated in FIG. 8 that the erase state E represents ‘1’ andthe program state P represents ‘0’.

Thereafter, when MSB data are received, an MSB program operation isperformed. In the MSB program operation, memory cells of the erase stateE are programmed to an erase state E or a first program state P1. Memorycells of the program state P are programmed to a second program state P2or a third program state P3. For example, it is illustrated in FIG. 8that the erase state E represents ‘11’, the first program state P1represents ‘01’, the second program state P2 represents ‘00’, and thethird program state P3 represents ‘10’.

When LSB data are received from the host, the state conversion unit 175performs a state-encode operation. For example, the state conversionunit 175 counts the number of 0's and the number of 1's of the receivedLSB data. The state conversion unit 175 compares the number of 0's andthe number of 1's. The state conversion unit 175 performs a state-encodeoperation according to the comparison result.

For example, the LSB data are state-encoded according the disturbancesby the memory cells programmed to the erase state E and the memory cellsprogrammed to the third program state P3.

For example, if the disturbance by the memory cells programmed to theerase state E is smaller than the disturbance by the memory cellsprogrammed to the third program state P3, the state conversion unit 175performs a state-encode operation so that the number of 1's of the LSBdata becomes greater than the number of 0's of the LSB data. That is, ifthe number of 1's of the LSB data is greater than the number of 0's ofthe LSB data, the state conversion unit 175 retains the LSB data. If thenumber of 1's of the LSB data is smaller than the number of 0's of theLSB data, the state conversion unit 175 inverts the LSB data.

As another example, if the disturbance by the memory cells programmed tothe erase state E is greater than the disturbance by the memory cellsprogrammed to the third program state P3, the state conversion unit 175performs a state-encode operation so that the number of 1's of the LSBdata becomes smaller than the number of 0's of the LSB data. That is, ifthe number of 1's of the LSB data is greater than the number of 0's ofthe LSB data, the state conversion unit 175 inverts the LSB data. If thenumber of 1's of the LSB data is smaller than the number of 0's of theLSB data, the state conversion unit 175 retains the LSB data.

For example, the state-encode operation for the LSB data is set by thestate conversion unit 175. For example, the state-encode operation forthe LSB data is set according to a value stored in a mode register (notillustrated) of the state conversion unit 175.

For example, it is assumed that the disturbance by the memory cellsprogrammed to the erase state E is smaller than the disturbance by thememory cells programmed to the third program state P3. That is, thestate conversion unit 175 performs a state-encode operation so that thenumber of 1's of the LSB data becomes greater than the number of 0's ofthe LSB data.

FIG. 9 illustrates state-converted LSB data.

In FIG. 9, the axis of abscissas (x-axis) represents logic states andthe axis of ordinates (y-axis) represents the number of data. Forexample, it is assumed that the lowest to highest logic states arerepresented along the direction of the axis of abscissas (x-axis). Forexample, it is assumed that the erase state E represents the lowestlogic state and the program state P represents the highest logic state.

When LSB data are received, the state conversion unit 175 converts theLSB data so that the number of 1's of the LSB data becomes greater thanthe number of 0's of the LSB data. For example, if the number of 0's ofthe LSB data is greater than the number of 1's of the LSB data, thestate conversion unit 175 inverts the LSB data. As another example, ifthe number of 1's of the LSB data is greater than the number of 0's ofthe LSB data, the state conversion unit 175 retains the LSB data. Thatis, in an LSB program operation, the number of erase states E becomesgreater than the number of program states P. Data illustrated in FIG. 9are programmed in the flash memory device 200.

When MSB data are received, the state conversion unit 175 state-encodesthe MSB data so that the number of memory cells to be programmed to thefirst program state P1 becomes greater than the number of memory cellsto be programmed to the erase state E and the number of memory cells tobe programmed to the second program state P2 becomes greater than thenumber of memory cells to be programmed to the third program state P3.

For example, it is illustrated in FIG. 9 that MSB data of the erasestate E are ‘1’, MSB data of the first program state P1 are ‘0’, MSBdata of the second program state P2 are ‘0’, and MSB data of the thirdprogram state P3 are ‘1’. That is, the MSB data of the erase state E andthe third program state P3 are ‘1’ and the MSB data of the first programstate P1 and the second program state P2 are ‘0’. The state conversionunit 175 state-encodes the MSB data so that the number of 0's of the MSBdata becomes greater than the number of 1's of the MSB data.

For example, if the number of 0's of the MSB data is greater than thenumber of 1's of the MSB data, the state conversion unit 171 retains theMSB data. If the number of 0's of the MSB data is smaller than thenumber of 1's of the MSB data, the state conversion unit 171 inverts theMSB data.

FIG. 10 illustrates state-converted MSB data.

In FIG. 10, the axis of abscissas (x-axis) represents logic states andthe axis of ordinates (y-axis) represents the number of data. Forexample, it is assumed that the lowest to highest logic states arerepresented along the direction of the axis of abscissas (x-axis). Forexample, it is assumed that the erase state E represents the lowestlogic state and the third program state P3 represents the highest logicstate.

When MSB data are received, the state conversion unit 175 converts theMSB data so that the number of 0's of the MSB data becomes greater thanthe number of 1's of the MSB data, For example, if the number of 1's ofthe MSB data is greater than the number of 0's of the MSB data, thestate conversion unit 175 inverts the MSB data.

Memory cells are programmed from “1’ of the LSB to ‘11’ or ‘01’. When anMSB program operation is performed, the number of 01's is greater thanthe number of 11's. That is, when a state conversion operation isperformed, the number of first program states P1 is always greater thanthe number of erase states E, thus reducing the disturbance by thememory cells programmed to the erase state E.

Memory cells are programmed from “0’ of the LSB to ‘00’ or ‘10’. When anMSB program operation is performed, the number of 00's is greater thanthe number of 10's. That is, when a state conversion operation isperformed, the number of third program states P3 is always greater thanthe number of second program states P2, thus reducing the disturbance bythe memory cells programmed to the third program state P3.

Relations between the logic states E, P1, P2 and P3 and logic values‘11’, ‘01’, ‘00’ and ‘10’ described referring to FIGS. 7 to 10 are justan embodiment. It will be understood that the relations between thelogic states E, P1, P2 and P3 and logic values ‘11’, ‘01’, ‘00’ and ‘10’can be applied and optimized in various forms. When the relationsbetween the logic states and the logic values changes, the stateconversion operation also changes.

For example, the state conversion operation may be changed that thestate conversion unit 175 converts the LSB data so that the number of1's of the LSB data becomes greater than the number of 0's of the LSBdata when LSB data are received, and the state conversion unit 175converts the MSB data so that the number of 0's of the MSB data becomesgreater than the number of 1's of the MSB data when the MSB data arereceived.

For example, the state conversion operation may be changed that thestate conversion unit 175 converts the LSB data so that the number of0's of the LSB data becomes greater than the number of 1's of the LSBdata when LSB data are received, and the state conversion unit 175converts the MSB data so that the number of 1's of the MSB data becomesgreater than the number of 0's of the MSB data when the MSB data arereceived.

For example, the state conversion operation may be changed that thestate conversion unit 175 converts the LSB data so that the number of0's of the LSB data becomes greater than the number of 1's of the LSBdata when LSB data are received, and the state conversion unit 175converts the MSB data so that the number of 0's of the MSB data becomesgreater than the number of 1's when the MSB data are received.

When a state-encode operation is performed, the state conversion unit175 generates conversion information CI. For example, the conversioninformation CI indicates whether the corresponding LSB data are invertedand whether the corresponding MSB data are inverted. When state-encodeddata are read from the flash memory device 200, the conversioninformation CI is read simultaneously. The state conversion unit 175uses the conversion information CI to state-decode the read data.

It is assumed that data to be written in the storage region RA (see FIG.6) of the flash memory device 200 is received in a random writeoperation. The state conversion unit 175 state-decodes the received dataand generates conversion information CI. The state-decoded data arewritten in the storage region RA, and the conversion information CI iswritten in a spare region corresponding to the storage region RA.

It is assumed that data are received from the storage region of theflash memory device 200 in a random read operation. At this point,conversion information CI corresponding to the data stored in thestorage region RA is simultaneously read from a spare regioncorresponding to the storage region RA. The state conversion unit 175uses the conversion information CI to state-decode the received data.

For example, the storage region RA is a sector. The spare region forstoring the conversion information CI is provided on a sector-by-sectorbasis. That is, it will be understood that the memory system 10 mayperform a random read/write operation on a sector-by-sector basis.However, it will be understood that the unit of a random read/writeoperation of the memory system 10 is not limited to being a sector.

FIGS. 11 to 13 are diagrams illustrating a state conversion operation ofthe controller 100 of FIG. 3 according to further embodiments.

In FIGS. 11 to 13, the axis of abscissas (x-axis) represents logicstates and the axis of ordinates (y-axis) represents the number of data.Each of the logic states is comprised of two bits. When data areprogrammed in a memory cell, the threshold voltage of the memory cellmay be determined according to the logic state represented by the data.

For example, it is assumed that data received from the host have statesas illustrated in FIG. 8. The state conversion unit 175 counts thenumber of the erase states E and the first to third program statesP1˜P3.

The state conversion unit 175 converts the states represented by data sothat the number of the third program states P3 becomes small. Forexample, the state conversion unit 175 converts the states representedby data so that the number of the third program states P3 becomessmallest among the numbers of the first to third program states P1˜P3.It is illustrated in FIG. 7 that the number of the second program statesP2 is the smallest among the numbers of the first to third programstates P1˜P3. The state conversion unit 175 exchanges the second programstate P2 and the third program state P3. That is, data representing thethird program state P3 are converted to represent the second programstate P2. Also, data representing the second program state P2 areconverted to represent the third program state P3. The state conversionresults are illustrated in FIG. 11.

Referring to FIG. 11, the number of the third program states P3 isreduced in comparison with the states of FIG. 7. Thus, the coupling andcharge loss by the memory cells programmed to the third program state P2may be reduced.

As another example, the state conversion unit 175 converts the states ofdata so that the number of the erase states E becomes smallest among thenumbers of the erase states E and the first and second program states P1and P2. It is illustrated in FIG. 7 that the number of the secondprogram states P2 is the smallest among the numbers of the erase statesE and the first and second program states P1 and P2. The stateconversion unit 175 exchanges the first program state P1 and the secondprogram state P2. That is, data representing the erase state E areconverted to represent the second program state P2. Also, datarepresenting the second program state P2 are converted to represent theerase state E. The state conversion results are illustrated in FIG. 12.

Referring to FIG. 12, the number of the erase states E is reduced incomparison with the states of FIG. 7. Thus, the read voltage disturbanceby the memory cells programmed to the erase state E is reduced.

As another example, the state conversion unit 175 converts the states ofreceived data so that the number of the erase states E and the thirdprogram states P3 becomes smaller than the number of the first andsecond program states P1 and P2. For example, the state conversion unit175 converts the states of data so that the number of the third programstates P3 becomes smallest and the number of the erase states E becomessecond-smallest. For example, the state conversion unit 175 exchangesthe second program state P2 and the third program state P3 and exchangesthe erase state E and the first program state P1.

That is, data representing the third program state P3 are converted torepresent the second program state P2, and data representing the secondprogram state P2 are converted to represent the third program state P3.Also, data representing the erase state E are converted to represent thefirst program state P1, and data representing the first program state P1are converted to represent the erase state E, The state conversionresults are illustrated in FIG. 13.

Referring to FIG. 13, the number of the third program states P3 and thenumber of the erase states E are reduced in comparison with the statesof FIG. 7. Thus, the disturbances by the memory cells programmed to thethird program state P3 and the erase state E are reduced.

It will be understood that the state conversion operation may beperformed in consideration of the effects of coupling, charge loss andread voltage disturbance so that the number of the erase state E issmallest and the number of the third program state P3 issecond-smallest. Also, it will be understood that the first and secondprogram states P1 and P2 may also be converted in consideration of theeffects of coupling, charge loss and read voltage disturbance.

In another example, the state conversion unit 175 converts the states ofdata so that the number of the erase states E becomes smallest and thenumber of the third program states P3 becomes second-smallest.

The state conversion unit 175 may generate conversion information CI onthe basis of the state-encode results. The conversion information CI mayinclude information about the state-encode operation. In a readoperation, read data and conversion information CI may be read from theflash memory device 200. The state conversion unit 175 may use the readconversion information CI to state-decode the read data.

As described above, the sequential data are randomized and the randomwrite data are state-converted. Thus, the reliability of data stored inthe flash memory device 200 may be improved.

As described above, the sequential data are randomized and the sparedata of the sequential data are state-converted. Thus, the reliabilityof not only the user data but also the spare data may be improved.

It has been described in the above embodiments that a state conversionoperation is performed in a random read/write operation. However, itwill be understood that a state conversion operation may also beperformed in a sequential read/write operation.

FIG. 14 is a block diagram of the flash memory device 200 of FIG. 2according to another embodiment of the inventive concept.

Referring to FIG. 14, the flash memory device 200 includes first andsecond planes 200 a and 200 b. The first and second planes 200 a and 200b may be read/written independently. In FIG. 14, read/write circuits,address decoders, data input/output circuits and control logic circuitscorresponding to the first and second planes 200 a and 200 b are omittedfor conciseness.

A first page Page1 is illustrated in the first plane 200 a, and a secondpage Page2 is illustrated in the second page 200 b. For example, it isassumed that the flash memory device 200 supports a multi-plane programfunction. The multi-plane program function is a function of programminga plurality of planes simultaneously.

For example, the first page Page1 and the second page Page2 aresimultaneously programmed in a multi-plane program operation of theflash memory device 200. For example, data to be programmed in the firstpage Page1 are loaded into the flash memory device 200 and data to beprogrammed in the second page Page2 are loaded in the flash memorydevice 200. Thereafter, the first and second pages Page1 and Page2 areprogrammed simultaneously. Thus, the program time of the first andsecond pages Page1 and Page 2 is reduced.

For example, it is assumed that the first and second pages Page1 andPage2 are physical pages. That is, the first page Page1 includes alowest page and a highest page. Also, the second page Page2 includes alowest page and a highest page.

FIG. 15 is a diagram illustrating an embodiment of loading data into theflash memory device 200 in a multi-plain program and state conversionoperation.

Referring to FIGS. 14 and 15, first page data PD1 are data to be writtenin the lowest page of the first page Page1. Second page data PD2 aredata to be written in the lowest page of the second page Page2. Thirdpage data PD3 are data to be written in the highest page of the firstpage Page1. Fourth page data PD4 are data to be written in the highestpage of the second page Page2. It is assumed that data are received inthe order of from the first page data PD1 to the fourth page data PD4.

As described with reference to FIGS. 11 and 13, four logic states arenecessary to perform a state conversion operation. That is, both of thelowest page data and the highest page data may be used to program onephysical page.

The controller 200 allocates the first page data PD1 as the lowest pagedata of the first page Page1 and allocates the second page data PD2 asthe highest page data of the first page Page1. Also, the controller 200allocates the third page data PD3 as the lowest page data of the secondpage Page2 and allocates the fourth page data PD4 as the highest pagedata of the second page Page2.

The first bit of the first page data PD1 and the first bit of the secondpage data PD2 represent a logic state to be written in the first memorycell of the first page Page1. Likewise, the k^(th) bit of the first pagedata PD1 and the k^(th) bit of the second page data PD2 represent alogic state to be written in the k^(th) memory cell of the first pagePage1. Thus, when the second page data PD2 start to be inputted, a stateconversion operation for the first page Page1 (e.g., an operation ofcounting the number of logic states) may start to be performed.

The first and second page data PD1 and PD2 are state-encoded to formfirst and second transformed page data TPD1 and TPD2. The firsttransformed page data TPD1 are transmitted to the flash memory device200 to be written in the lowest page of the first page Page1. The secondtransformed page data TPD2 are transmitted to the flash memory device200 to be written in the highest page of the first page Page1.

The third and fourth page data PD3 and PD4 are received andstate-converted while the first and second transformed page data TPD1and TPD2 are transmitted to the flash memory device 200. The third andfourth page data PD3 and PD4 are state-encoded to form third and fourthtransformed page data TPD3 and TPD4. Upon completion of the transmissionof the first and second transformed page data TPD1 and TPD2, thethird/fourth transformed page data TPD3/TPD4 are transmitted to theflash memory device 200 to be written in the lowest/highest page of thesecond page Page2.

A first time delay ΔT1 may occur until the output of the firsttransformed page data TPD1 after the input of the first page data PD01.However, as described above, the first and second transformed page dataTPD1 and TPD2 may be generated when the second page data PD2 arereceived. The third and fourth page data PD3 and PD4 are received whilethe first and second transformed page data TPD1 and TPD2 are outputted.The third and fourth transformed page data TPD3 and TPD4 may begenerated when the third and fourth page data PD3 and PD4 are received.Upon completion of the output of the second transformed page data TPD2,the third transformed page data TPD3 may be outputted without delay.That it, the reception of the page data PD1˜PD4 and the output of thetransformed page data TPD1˜TPD4 are performed in a pipeline manner.Thus, except the initial first time delay ΔT1, there is no delay in thestate conversion operation.

FIG. 16 is a diagram illustrating further embodiments of loading datainto the flash memory device 200 in a multi-plain program and stateconversion operations.

Referring to FIGS. 14 and 16, first page data PD1 are data to be writtenin the lowest page of the first page Page1. Second page data PD2 aredata to be written in the lowest page of the second page Page2 . Thirdpage data PD3 are data to be written in the highest page of the firstpage Page1. Fourth page data PD4 are data to be written in the highestpage of the second page Page2. It is assumed that data are received inthe order of from the first page data PD1 to the fourth page data PD4.

As described with reference to FIGS. 11 and 13, four logic states arenecessary to perform a state conversion operation. That is, both of thelowest page data and the highest page data are necessary to program onephysical page.

The controller 200 allocates the first page data PD1 as the lowest pagedata of the first page Page1 and allocates the second page data PD2 asthe lowest page data of the second page Page2. Also, the controller 200allocates the third page data PD3 as the highest page data of the firstpage Page1 and allocates the fourth page data PD4 as the highest pagedata of the second page Page2.

The first bit of the first page data PD1 and the first bit of the thirdpage data PD3 represent a logic state to be written in the first memorycell of the first page Page1. Likewise, the k^(th) bit of the first pagedata PD1 and the k^(th) bit of the third page data PD3 represent a logicstate to be written in the k^(th) memory cell of the first page Page1.Thus, when the third page data PD3 start to be inputted, a stateconversion operation for the first page Page1 (e.g., an operation ofcounting the number of logic states) may start to be performed.Likewise, when the fourth page data PD4 start to be inputted, a stateconversion operation for the second page Page2 (e.g., an operation ofcounting the number of logic states) may start to be performed.

The first and third page data PD1 and PD3 are state-encoded to formfirst and second transformed page data TPD1 and TPD2. The firsttransformed page data TPD1 are transmitted to the flash memory device200 to be written in the lowest page of the first page Page1. The secondtransformed page data TPD2 are transmitted to the flash memory device200 to be written in the highest page of the first page Page1.

The fourth page data PD4 are received and the second and fourth pagedata PD2 and PD4 are state-converted while the first and secondtransformed page data TPD1 and TPD2 are transmitted to the flash memorydevice 200. The second and fourth page data PD2 and PD4 arestate-encoded to form third and fourth transformed page data TPD3 andTPD4. Upon completion of the transmission of the first and secondtransformed page data TPD1 and TPD2, the third/fourth transformed pagedata TPD3/TPD4 are transmitted to the flash memory device 200 to bewritten in the lowest/highest page of the second page Page2.

A second time delay ΔT2 may occur until the output of the firsttransformed page data TPD1 after the input of the first page data PD1.However, as described above, the first and second transformed page dataTPD1 and TPD2 may be generated when the third page data PD3 arereceived. The fourth page data PD4 are received while the first andsecond transformed page data TPD1 and TPD2 are outputted. The third andfourth transformed page data TPD3 and TPD4 may be generated when thefourth page data PD4 are received. Upon completion of the output of thesecond transformed page data TPD2, the third transformed page data TPD3may be outputted without delay. That it, the reception of the page dataPD1˜PD4 and the output of the transformed page data TPD1˜TPD4 areperformed in a pipeline manner. Thus, except the initial second timedelay ΔT2, there may be no significant delay in the state conversionoperation.

It will be understood that the loading operation described withreference to FIGS. 15 and 16 may also be applicable in a random-encodeoperation. For example, when the second page data PD2 start to bereceived, the first and second page data PD1 and PD2 are random-encoded.For example, the first page data PD1 and the second page data PD2 areprovided to the operation circuit 174 of FIG. 5. The first and secondpage data PD1 and PD2 are random-encoded to form first and secondtransformed page data TPD1 and TPD2.

As another example, when the third page data PD3 start to be received,the first and third page data PD1 and PD3 are random-encoded. Forexample, the first page data PD1 and the third page data PD3 areprovided to the operation circuit 174 of FIG. 5. The first and thirdpage data PD1 and PD3 are random-encoded to form first and secondtransformed page data TPD1 and TPD2.

FIG. 17 is a block diagram of a flash memory device 300 according tofurther embodiments.

Referring to FIG. 17, a flash memory device 300 includes a memory cellarray 310, an address decoder 320, a read/write circuit 330, a datainput/output (I/O) circuit 340, a control logic circuit 350, and anencoding/decoding unit 360.

The memory cell array 310, the address decoder 320, the read/writecircuit 330, the data I/O circuit 340 and the control logic circuit 350operate in the same manner as the memory cell array 210, the addressdecoder 220, the read/write circuit 230, the data I/O circuit 240 andthe control logic circuit 250 described with reference to FIG. 2. Thus,a detailed description thereof will be omitted for conciseness.

In comparison with the flash memory device 200 of FIG. 2, the flashmemory device 300 of FIG. 17 further includes the encoding/decoding unit360. That is, an encoding/decoding operation is performed not by thecontroller 100 but by the flash memory device 300. The encoding/decodingunit 360 includes a randomization unit 361 and a state conversion unit365. The randomization unit 361 is configured to perform arandom-encode/decode operation as described with reference to FIGS. 3 to5. The state conversion unit 365 operates in a similar manner asdescribed with reference to FIGS. 3, 4 and 6 to 16. Thus, a detaileddescription thereof will be omitted for conciseness.

FIG. 18 is a block diagram of a computing system including the memorysystem 10 of FIG. 1 according to an embodiment of the inventive concept.

Referring to FIG. 18, a computing system 400 according to an embodimentof the inventive concept includes a central processing unit (CPU) 410, arandom access memory (RAM) 420, a user interface 430, a power supplyunit 440, and a memory system 10.

The memory system 10 is electrically connected through a system bus 450to the CPU 410, the RAM 420, the user interface 430, and the powersupply unit 440. Data, which are provided through the user interface 430or processed by the CPU 410, are stored in the memory system 10. Thememory system 10 includes a controller 100 and a nonvolatile memorydevice 200/300 of FIG. 2/17.

When the memory system 10 is used for a solid state disk (SSD), thebooting speed of the computing system 400 may increase remarkably.Although not illustrated in FIG. 18, those skilled in the art willreadily understand that the computing system 400 may further include anapplication chipset and a camera image processor.

According to the inventive concept described above, data are randomizedor state-converted prior to storage. Thus, the reliability of userdevices (or semiconductor memory devices) is improved.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

What is claimed is:
 1. A memory controller comprising: a first interfaceunit configured to exchange data with an external device; a processorconfigured to determine, in response to data received through the firstinterface unit, whether to randomize or state-convert the received datato generate randomized data or state-converted data in response to acomparison of a size of the received data with a size of one page of aflash memory; and a second interface unit configured to receive therandomized data or the state-converted data from the processor and tostore the randomized data or the state-converted data in the flashmemory.
 2. A method of operating a memory controller including a firstinterface unit configured to exchange data with an external device and asecond interface unit configured to exchange data with a flash memory,the method comprising: determining, in response to data received throughthe first interface unit, whether to randomize or state-convert thereceived data to generate randomized data or state-converted data inresponse to a comparison of a size of the received data with a size ofone page of a flash memory; and storing the randomized data or thestate-converted data in the flash memory.